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1 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 features n 25 expanded register files n 47 input/output lines (Z89165) 31 input/output lines (z89166) 43 input/output lines (core processor) n six vectored, prioritized z8 interrupts with programmable polarity n three vectored, prioritized dsp interrupts with programmable polarity n two analog comparators n two programmable z8 8-bit counter/timers, each with two 6-bit programmable prescaler n watch-dog timer /power-on reset n on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc, or external clock drive n ram and rom protect, low-emi option c ustomer p rocurement s pecification n part z8 rom z8 ram* speed number (kbytes) (kbytes) (mhz) Z89165 24 236 20 z89166 romless 236 20 z89167 24 236 24 z89168 romless 236 24 z89169 32 236 24 *general-purpose n part dsp rom dsp ram speed number (words) (words) (mhz) Z89165 6k 512 20 z89166 6k 512 20 z89167 8k 512 24 z89168 8k 512 24 z89169 8k 512 24 n 68- and 84-pin plcc packages n 4.5- to 5.5-volt operating range n low-power consumption (200 mw typical) n 0 c to +70 c temperature range general description zilog's digital voice processor controller family combines a z8 ? microcontroller and a dsp processor on-chip for a cost-effective turnkey system in digital telephone answering devices and other voice processing applications. the dual-processor architecture is loosely coupled by mailbox registers and an interrupt system, enabling dsp or z8 programs to be directed by events in each other's domain. the z8 microcontroller uses an expanded register file to allow access to register-mapped peripheral and i/o circuits for programming versatility. the 16-bit dsp processor features a 24-bit alu and accumulator with single-cycle instructions, providing the algorithm processing power necessary for telephone voice quality. Z89165/167/169 and z89166/168 (rom less ) e nhanced d ual -p rocessor dtad c ontrollers the Z89165/166 devices offer a half-flash 8-bit a/d converter with up to 128 khz sample rate and a 10-bit pulse-width modulator (pwm) d/a converter, eliminating the need for an external codec. the z89167/168/169 devices feature a hardware aram interface, as well as a dual-codec interface. a 10-bit pwm d/a converter is also on-chip. notes: all signals with a preceding front slash, "/", are active low, e.g.: b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss
2 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog general description (continued) port 0 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p31 p32 p33 p40 p41 p42 p43 p44 p45 p46 p47 p50 p51 p52 p53 p54 p55 p56 p57 rmls /as /ds r/w timer 0 capture reg. port 3 port 1 port 4 port 2 port 5 timer 1 register file 256 x 8 bit 24 kbytes program rom (Z89165) z8 core register bus internal address bus internal data bus expanded register file (z8) peripheral register (dsp) expanded register bus extended bus of the dsp 6k words program rom dsp core internal address bus internal data bus dsp port pwm (10-bit) adc (8-bit) timer 2 timer 3 extended bus of the dsp ext. memory control osc power xtal1 xtal2 vdd gnd /reset int 1 int 2 dsp0 dsp1 an in an vdd an gnd vref+ vref- pwm 256 word ram 0 256 word ram 1 p34 p35 p36 p37 input output i/o (bit programmable) i/o (bit programmable) address or i/o (nibble programmable) address/data or i/o (byte programmable) i/o (bit programmable) mailbox Z89165/166 functional block diagram
3 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 port 0 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p40 p41 p42 p43 p44 p45 p46 p47 p50 p51 p52 p53 timer0 port 4 port 1 port 5 port 2 aram controller timer1 register file 256 x 8-bit 24 kbytes (167) 32 kbytes (169) program rom z8 core internal register bus timer3 timer2 power aram control i/o (bit programmable) /ras /cas aram_r/w aram_/oe address or i/o (nibble programmable) address/data or i/o (byte programmable) i/o (bit programmable) din dena0 dclk dout dena1 pwm (10-bit) port 3 i/o (bit programmable) internal address bus internal data bus 8k words program rom address bus data bus dsp core peripheral registers (dsp) extended register file (z8) peripheral data bus of the dsp mailbox data0 data1 data2 data3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 aram_sel0 aram_sel1 input output p31 p32 p33 p34 p35 p36 p37 codec interface rmls /as /ds r/w z8 ext. memory control pwm /reset vdd gnd -5v control out -5v osc xtal1 xtal2 general description (continued) z89167/168/169 functional block diagram
4 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog Z89165 68-pin plcc pin identification z89166 68-pin plcc pin identification pin name function direction +5v power 5v power input (digital power) gnd power device ground (digital ground) an ain 8-bit a to d converter input vrefC ain low reference level for a to d converter vref+ ain high reference level for a to d converter an vdd power adc +5v power (analog power) an gnd power adc ground (analog ground) p00-p07 data i/o general-purpose i/o port p10-p17 data i/o general-purpose i/o port p20-p27 data i/o general-purpose i/o port pin identification pin name function direction p31-p37 data i/o general-purpose i/o port p40-p47 data i/o general-purpose i/o port p50-p57 data i/o general-purpose i/o port dsp0-dsp1 data 0 general-purpose 0 port xtal1 osc1 20.48 mhz crystal oscillator input xtal2 osc2 20.48 mhz crystal oscillator input /reset i/o system reset pwm out 10-bit pwm, 5v ttl output Z89165 7 8 9 654321 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p31 p32 p33 p34 vdd p35 p14 dsp1 dsp0 p36 p13 p37 p40 p12 p06 p41 p42 vref+ anin vref- angnd /as /reset r//w pwm p10 p47 p11 p46 p53 p45 p44 p43 n/c xtal2 xtal1 p22 p56 p23 p55 p54 gnd p17 p05 p24 p16 p25 p15 p26 p27 n/c p00 p01 p02 p03 p57 p50 p04 vdd rmls /ds p51 p52 p21 p20 p07 gnd anvdd pin description z89166 7 8 9 654321 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p31 p32 p33 p34 vdd p35 p14 dsp1 dsp0 p36 p13 p37 p40 p12 p06 p41 p42 vref+ anin vref- angnd /as /reset r//w pwm p10 p47 p11 p46 p53 p45 p44 p43 /sync xtal2 xtal1 p22 p56 p23 p55 p54 gnd p17 p05 p24 p16 p25 p15 p26 p27 sclk p00 p01 p02 p03 p57 p50 p04 vdd vdd /ds p51 p52 p21 p20 p07 gnd anvdd
5 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 184 z89168 84-pin plcc 33 42 43 32 53 54 11 12 75 74 vcc addr0 addr1 addr2 addr4 addr5 addr6 addr7 addr8 addr9 addr10 aram_sel0 aram_sel1 d ata 0 d ata 1 d ata 2 d ata 3 /ras /cas gnd vcc c_cloc k c_en0 c_en1 p50 p51 p52 p53 out_5v gnd /as p37 p36 p35 p34 p33 p32 p31 pwm p10 gnd p11 p12 p13 r/w p14 p15 p16 p17 vcc vcc p00 p01 p02 p03 p04 p05 p06 p07 /reset aram_r/w aram_oe addr3 xtal1 xtal2 p27 p26 p24 p23 p22 p21 p20 /ds p47 p46 p45 p44 p43 p42 p41 p40 c_din c_dou t p25 pin description (continued) z89168 84-pin plcc pin identification
6 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog pin description (continued) z89168 84-pin plcc pin identification i/o port functions pin number i/o function v ss 32, 54, 65 digital ground v cc 12, 44, 74, 45 digital vcc = +5 v p00-p07 43-36 input/output p00-p07 (general-purpose nibble programmable i/o port.) p10-p17 55, 53-51, 49-46 input/output p10-p17 (general-purpose byte programmable i/o port.) p20-p27 2-9 input/output p20-p27 (general-purpose bit programmable i/o.) p31-p37 57-63 input/output p31-p37 (general-purpose i/o port. bits p31-p33 are inputs, while bits p34-p37 are outputs.) p40-p47 77-84 input/output p40-p47 (general-purpose bit programmable i/o.) p50-p53 70-67 input/output p50-p53 (general-purpose bit programmable i/o.) c_din 76 input data input from codec. c_dout 75 output data output to codec. c_clock 73 output codec clock (2.048 mhz) c_ena0 72 output codec 0 enable (8 khz) c_ena1 71 output codec 1 enable (8 khz) pwm 56 output pulse width modulator output data0 26 input/output data 0 i/o of the aram interface data1 27 input/output data 1 i/o of the aram interface data2 28 input/output data 2 i/o of the aram interface data3 29 input/output data 3 i/o of the aram interface addr0 13 output address 0 line of the aram interface addr1 14 output address 1 line of the aram interface addr2 15 output address 2 line of the aram interface addr3 16 output address 3 line of the aram interface addr4 17 output address 4 line of the aram interface addr5 18 output address 5 line of the aram interface addr6 19 output address 6 line of the aram interface addr7 20 output address 7 line of the aram interface addr8 21 output address 8 line of the aram interface addr9 22 output address 9 line of the aram interface addr10 23 output address 10 line of the aram interface for 4 meg arams. select 2 output of aram interface for 1 meg arams support. the latter mode is used to switch between different pages of aram. aram_sel0 24 output select 0 output of aram interface. used to switch between different pages of aram. aram_sel1 25 output select 1 output of aram interface. used to switch between different pages of aram. /ras 30 output row address strobe of aram interface. /cas 31 output column address strobe of aram interface. aram_r/w 34 output read/write strobe of aram interface. aram_/oe 33 output output enable strobe of aram interface. xtal1 11 input 24.57 mhz crystal input xtal2 10 output 24.57 mhz crystal output /reset 35 input /reset input r/w 50 output z8 ? external memory interface r/w output /as 64 output z8 external memory interface /as output /ds 1 output z8 external memory interface /ds output
7 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 184 z89c169/z89c167 84-pin plcc 33 42 43 32 53 54 11 12 75 74 vcc addr0 addr1 addr2 addr4 addr5 addr6 addr7 addr8 addr9 addr10 aram_sel0 aram_sel1 d ata 0 d ata 1 d ata 2 d ata 3 /ras /cas gnd vcc c_cloc k c_en0 c_en1 p50 p51 p52 p53 out_5v gnd /as p37 p36 p35 p34 p33 p32 p31 pwm p10 gnd p11 p12 p13 r/w p14 p15 p16 p17 rmls vcc p00 p01 p02 p03 p04 p05 p06 p07 /reset aram_r/w aram_oe addr3 xtal1 xtal2 p27 p26 p24 p23 p22 p21 p20 /ds p47 p46 p45 p44 p43 p42 p41 p40 c_din c_dou t p25 pin description (continued) z89167/169 84-pin plcc pin identification
8 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog pin description (continued) z89169/z89167 84-pin plcc, pin identification i/o port functions pin number i/o function v ss 32, 54, 65 digital ground v cc 12, 44, 74 digital vcc = +5 v p00-p07 43-36 input/output p00-p07 (general-purpose nibble programmable i/o port.) p10-p17 55, 53-51, 49-46 input/output p10-p17 (general-purpose byte programmable i/o port.) p20-p27 2-9 input/output p20-p27 (general-purpose bit programmable i/o.) p31-p37 57-63 input/output p31-p37 (general-purpose i/o port. bits p31-p33 are inputs, while bits p34-p37 are outputs.) p40-p47 77-84 input/output p40-p47 (general-purpose bit programmable i/o.) p50-p53 70-67 input/output p50-p53 (general-purpose bit programmable i/o.) c_din 76 input data input from codec. c_dout 75 output data output to codec. c_clock 73 output codec clock (2.048 mhz) c_ena0 72 output codec 0 enable (8 khz) c_ena1 71 output codec 1 enable (8 khz) pwm 56 output pulse width modulator output data0 26 input/output data 0 i/o of the aram interface data1 27 input/output data 1 i/o of the aram interface data2 28 input/output data 2 i/o of the aram interface data3 29 input/output data 3 i/o of the aram interface addr0 13 output address 0 line of the aram interface addr1 14 output address 1 line of the aram interface addr2 15 output address 2 line of the aram interface addr3 16 output address 3 line of the aram interface addr4 17 output address 4 line of the aram interface addr5 18 output address 5 line of the aram interface addr6 19 output address 6 line of the aram interface addr7 20 output address 7 line of the aram interface addr8 21 output address 8 line of the aram interface addr9 22 output address 9 line of the aram interface addr10 23 output address 10 line of the aram interface for 4 meg arams. select 2 output of aram interface for 1 meg arams support. the latter mode is used to switch between different pages of aram. aram_sel0 24 output select 0 output of aram interface. used to switch between different pages of aram. aram_sel1 25 output select 1 output of aram interface. used to switch between different pages of aram. /ras 30 output row address strobe of aram interface. /cas 31 output column address strobe of aram interface. aram_r/w 34 output read/write strobe of aram interface. aram_/oe 33 output output enable strobe of aram interface. xtal1 11 input 24.57 mhz crystal input xtal2 10 output 24.57 mhz crystal output romless 45 input z8 ? romless mode input (p0 and p1 are switched to d/a mode if this pin is connected to vcc). internally this pin is tight to gnd. /reset 35 inputoutput /reset input/output r/w 50 output z8 external memory interface r/w output /as 64 output z8 external memory interface /as output /ds 1 output z8 external memory interface /ds output
9 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 notes: * voltage on all pins with respect to gnd. ? see ordering information. symbol description min max units v cc supply voltage (*) C0.3 +7.0 v t stg storage temp C65 +150 c t a oper ambient temp ? c power dissipation 2.2 w stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. absolute maximum ratings standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (test load diagram). +5v from output under test 150 pf 9.1 k w 2.1 k w test load diagram capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins to gnd. parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf dc electrical characteristics v cc t a = 0 c to +70 c typical sym parameter note [1] min max @ 25 c units notes i cc supply current 5.0 v 65 40 ma i cc1 halt mode current 5.0 v 20 6 ma i cc2 stop mode current [2] notes: [1] 5.0v 0.5v. [2] the typical stop mode current value is 500 m a. the transient characteristics of the stop mode current will vary according to the application and should be validated in the specific application by the customer.
10 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog dc electrical characteristics Z89165/z89166 t a = 0 c typical v cc to +70 @ sym parameter note [1] min max 25 c units conditions v max max input voltage 5.0v 7 v i in = 250 m a v ch clock input high voltage 5.0v 0.9 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 5.0v gnd-0.3 0.1 v cc 1.5 v driven by external clock generator v ih input high voltage 5.0v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 5.0v gnd-0.3 0.2 v cc 1.5 v v oh output high voltage 5.0v v cc -0.4 4.8 v i oh = -2.0 ma (does not include xtal2) v ol1 output low voltage 5.0v 0.4 0.1 v i oh = +4.0 ma v ol2 output low voltage 5.0v 1.2 0.3 v i ol = +12 ma, 3 pin max (does not include xtal2) v rh reset input high voltage 5.0v 0.8 v cc v cc 2.1 v v rl reset input low voltage 5.0v gnd-0.3 0.2 v cc 1.7 v v offset comparator input offset 5.0v 25 10 mv voltage i il input leakage 5.0v -5 5 <5 m av in = ov, v cc i ol output leakage 5.0v -5 5 <5 m av in = ov, v cc i ir reset input current 5.0v -55 -30 m a notes: [1] 5.0 10% (v).
11 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 Z891650a additional dc electrical characteristics 1. a/d converter: absolute input current values symbol parameter maximum notes i il anin 40 m a i ih anin 2 m a i input vref+ 1.1 ma with vrefC = 0v vref+ = 5.5v 80 m a with vrefC = vref+ vref+ = 5.5v i input vrefC 1.1 ma with vref+ = 5.5v vrefC = 0v 80 m a with vref+ = vref+ vrefC = 0v the following parameters should be verified on the ate under these conditions: 5.5v @ 25 c. 2. other pins pin under test value additional condition romless pin i ih (max) = 6 m a no reset i il (max) = 6 m a no reset i ih (max) = 1ma during reset xtal1 i ih (max) = 30 m a while xtal2 = 0v no reset i il (max) = 30 m a while xtal2 = 5.5v no reset xtal2 i ih (max) = 10 m a while xtal1 = 0v stop mode invoked i il (max) = 10 m a while xtal2 = 5v stop mode invoked i ih (max) = 1 ma while xtal1 = 0v no reset i il (max) = 1 ma while xtal2 = 5v no reset i ih (max) = 4 ma while xtal1 = 0v during reset i il (max) = 4 ma while xtal2 = 5v during reset i ol (min) = 2 ma v ol = 1v v dd = 4.5v temp = 70 c i oh (min) = -1ma v oh = v dd -1v v dd = 4.5v temp = 70 c i ol (max) = 7 ma v ol = 1v v dd = 5.5v temp = 0 c i oh (max) = 6ma v oh = v dd -1v v dd = 5.5v temp = 0 c p31, p32, p33 i ih (max) = 1 m a (max) = 1 m a
12 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog dc electrical characteristics z89167/168/169 t a = 0 c to +70 c typical units sym parameter v cc min max 25 c at conditions notes max input voltage 4.5v 7 v i in 250 ua 5.5v 7 v i in 250 ua v ch clock input high voltage 4.5v 0.9 v cc v cc +0.3 1.3 v driven by external clock generator 5.5v 0.9 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 4.5v gnd-0.3 0.1 v cc 0.7 v driven by external clock generator 5.5v gnd-0.3 0.1 v cc 1.5 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 1.3 v 5.5v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 4.5v gnd-0.3 0.2 v cc 0.7 v 5.5v gnd-0.3 0.2 v cc 1.5 v v oh output high voltge 4.5v v cc -0.4 3.1 v i oh = -2.0 ma [1] 5.5v v cc -0.4 4.8 v i oh = -2.0 ma v ol1 output low voltage 4.5v 0.6 0.2 v i oh = +4.0 ma 5.5v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 4.5v 1.2 0.3 v i ol = +6 ma, 3 pin max 5.5v 1.2 0.3 v i ol = +12 ma, 3 pin max v rh reset input high voltage 4.5v .8 v cc v cc 1.5 v 5.5v .8 v cc v cc 2.1 v v rl reset input low voltage 4.5v gnd-0.3 0.2 v cc 1.1 5.5v gnd-0.3 0.2 v cc 1.7 v offset comparator input offset 4.5v 25 10 mv voltage 5.5v 25 10 mv i il input leakage 4.5v -5 5 <5 m av in = ov, v cc 5.5v -5 5 <5 m av in = ov, v cc i ol output leakage 4.5v -5 5 <5 m av in = ov, v cc 5.5v -5 5 <5 m av in = ov, v cc i ir reset input current 4.5v -45 -20 m a 5.5v -55 -30 m a note: [1] p10, p11 are measured at 4.5v only.
13 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 ac characteristics external i/o or memory read and write timing diagram r//w 9 12 19 3 16 13 4 5 8 18 11 6 17 10 15 7 14 2 1 port 0, /dm port 1 /as /ds (read) port1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 external i/o or memory read/write timing
14 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog ac characteristics Z89165/166 external i/o or memory read and write timing table v cc t a =0 c to +70 c no symbol parameter note [4] min max units notes 1 tda(as) address valid to /as rise delay 5.0v 25 ns [2,3] 2 tdas(a) /as rise to address float delay 5.0v 35 ns [2,3] 3 tdas(dr) /as rise to read data reqd valid 5.0v 150 ns [1,2,3] 4 twas /as low width 5.0v 35 ns [2,3] 5 tdaz(ds) address float to /ds fall 5.0v -3 ns 6 twdsr /ds (read) low width 5.0v 125 ns [1,2,3] 7 twdsw /ds (write) low width 5.0v 75 ns [1,2,3] 8 tddsr(dr) /ds fall to read data reqd valid 5.0v 90 ns [1,2,3] 9 thdr(ds) read data to /ds rise hold time 5.0v 0 ns [2,3] 10 tdds(a) /ds rise to address active delay 5.0v 40 ns [2,3] 11 tdds(as) /ds rise to /as fall delay 5.0v 35 ns [2,3] 12 tdr/w(as) r//w valid to /as rise delay 5.0v 25 ns [2,3] 13 tdds(r/w) /ds rise to r//w not valid 5.0v 35 ns [2,3] 14 tddw(dsw) write data valid to /ds fall (write) delay 5.0v 40 ns [2,3] 15 tdds(dw) /ds rise to write data not valid delay 5.0v 25 ns [2,3] 16 tda(dr) address valid to read data reqd valid 5.0v 180 ns [1,2,3] 17 tdas(ds) /as rise to /ds fall delay 5.0v 48 ns [2,3] 18 tddi(ds) data input setup to /ds rise 5.0v 50 ns [1,2,3] 19 tddm(as) /dm valid to /as fall delay 5.0v 20 ns [2,3] notes: [1] when using extended memory timing add 2 tpc. [2] timing numbers given are for minimum tpc. [3] see clock cycle dependent characteristics table. [4] 5.0 v 0.5 v. standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0.
15 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 ac characteristics z89167/168/169 external i/o or memory read and write timing table v cc t a =0 c to +70 c no symbol parameter note [4] min max units notes 1 tda(as) address valid to /as rise delay 5.0v 18 ns [2,3] 2 tdas(a) /as rise to address float delay 5.0v 22 ns [2,3] 3 tdas(dr) /as rise to read data reqd valid 5.0v 130 ns [1,2,3] 4 twas /as low width 5.0v 28 ns [2,3] 5 tdaz(ds) address float to /ds fall 5.0v 0 ns 6 twdsr /ds (read) low width 5.0v 90 ns [1,2,3] 7 twdsw /ds (write) low width 5.0v 62 ns [1,2,3] 8 tddsr(dr) /ds fall to read data reqd valid 5.0v 55 ns [1,2,3] 9 thdr(ds) read data to /ds rise hold time 5.0v 0 ns [2,3] 10 tdds(a) /ds rise to address active delay 5.0v 36 ns [2,3] 11 tdds(as) /ds rise to /as fall delay 5.0v 25 ns [2,3] 12 tdr/w(as) r//w valid to /as rise delay 5.0v 18 ns [2,3] 13 tdds(r/w) /ds rise to r//w not valid 5.0v 22 ns [2,3] 14 tddw(dsw) write data valid to /ds fall (write) delay 5.0v 18 ns [2,3] 15 tdds(dw) /ds rise to write data not valid delay 5.0v 23 ns [2,3] 16 tda(dr) address valid to read data reqd valid 5.0v 160 ns [1,2,3] 17 tdas(ds) /as rise to /ds fall delay 5.0v 32 ns [2,3] 18 tddi(ds) data input setup to /ds rise 5.0v 28 ns [1,2,3] 19 tddm(as) /dm valid to /as fall delay 5.0v 18 ns [2,3] notes: [1] when using extended memory timing add 2 tpc. [2] timing numbers given are for minimum tpc. [3] see clock cycle dependent characteristics table. [4] 5.0 v 0.5 v. standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0.
16 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog ac electrical characteristics additional timing diagram clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 clock setup 10 9 stop mode recovery source additional timing
17 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 ac electrical characteristics Z89165/166 additional timing table v cc t a =0 c to +70 c no symbol parameter note [6] min max units notes 1 tpc input clock period 5.0 v 48.83 ns [1] 2 trc,tfc clock input rise & fall times 5.0 v 6 ns [1] 3 twc input clock width 5.0 v 17 ns [1] 4 twtinl timer input low width 5.0 v 70 ns 5 twtinh timer input high width 5.0 v 3tpc [1] 6 tptin timer input period 5.0 v 8tpc [1] 7 trtin, timer input rise & fall timer 5.0 v 100 ns [1] tftin 8a twil int. request low time 5.0 v 70 ns [1,2] 8b twil int. request low time 5.0 v 3tpc [1] 9 twih int. request input high time 5.0 v 3tpc [1] 10 twsm stop-mode recovery width spec 5.0 v 12 ns [1] 5tpc 11 tost oscillator startup time 5.0 v 5tpc [3] 12 twdt watch-dog timer 5.0 v 3 ms d1=0, d0 = 0 [4] 5.0 v 6 ms d1=0, d0 = 1 [4] 5.0 v 12 ms d1=1, d0 = 0 [4] 5.0 v 50 ms d1=1, d0 = 1 [4] notes: [1] timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. [2] interrupt request via port 3 (p31-p33). [3] smr-d5 = 0. [4] reg. wdt. [5] 5.0v 0.5v.
18 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog ac electrical characteristics z89167/168/169 additional timing table v cc t a =0 c to +70 c no symbol parameter note [5] min max units notes 1 tpc input clock period 5.0 v 41.67 ns [1] 2 trc,tfc clock input rise & fall times 5.0 v 6 ns [1] 3 twc input clock width 5.0 v 16 ns [1] 4 twtinl timer input low width 5.0 v 70 ns 5 twtinh timer input high width 5.0 v 3tpc [1] 6 tptin timer input period 5.0 v 8tpc [1] 7 trtin, timer input rise & fall timer 5.0 v 100 ns [1] tftin 8a twil int. request low time 5.0 v 70 ns [1,2] 8b twil int. request low time 5.0 v 3tpc [1] 9 twih int. request input high time 5.0 v 3tpc [1] 10 twsm stop-mode recovery width spec 5.0 v 12 ns [1] 5tpc 11 tost oscillator startup time 5.0 v 5tpc [3] 12 twdt watch-dog timer 5.0 v 5 ms d1=0, d0 = 0 [4] 5.0 v 15 ms d1=0, d0 = 1 [4] 5.0 v 25 ms d1=1, d0 = 0 [4] 5.0 v 100 ms d1=1, d0 = 1 [4] notes: [1] timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. [2] interrupt request via port 3 (p31-p33). [3] smr-d5 = 0. [4] reg. wdt. [5] 5.0v 0.5v.
19 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 input handshake timing data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11 output handshake timing data in 1 3 4 5 6 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 2 ac electrical characteristics handshake timing diagrams
20 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog ac electrical characteristics Z89165/166 handshake timing table v cc t a =0 c to +70 c data no symbol parameter note [1] min max units direction 1 tsdi(dav) data in setup time 5.0 v 0 ns in 2 thdi(rdy) rdy to data hold time 5.0 v 0 ns in 3 twdav data available width 5.0 v 40 ns in 4 tddavi(rdy) dav fall to rdy fall delay 5.0 v 70 ns in 5 tddavid(rdy) dav rise to rdy rise delay 5.0 v 40 ns in 6 tddo(dav) rdy rise to dav fall delay 5.0 v 0 ns in 7 tcldav0(rdy) data out to dav fall delay 5.0 v tpc ns out 8 tcldav0(rdy) dav fall to rdy fall delay 5.0 v 0 ns out 9 tdrdy0(dav) rdy fall to dav rise delay 5.0 v 70 ns out 10 twrdy rdy width 5.0 v 40 ns out 11 tdrdy0d(dav) rdy rise to dav fall delay 5.0 v 40 ns out notes: [1] 5.0 v 0.5 v ac electrical characteristics z89167/168/169 handshake timing table v cc t a =0 c to +70 c data no symbol parameter note [1] min max units direction 1 tsdi(dav) data in setup time 5.0 v 0 ns in 2 thdi(rdy) ready to data in hold time 5.0 v 0 ns in 3 twdav data available width 5.0 v 110 ns in 4 tddavi(rdy) dav fall to rdy fall delay 5.0 v 115 ns in 5 tddavid(rdy) dav rise to rdy rise delay 5.0 v 80 ns in 6 tddo(dav) rdy rise to dav fall delay 5.0 v 0 ns in 7 tcldav0(rdy) data out to dav fall delay 5.0 v 25 ns out 8 tcldav0(rdy) dav fall to rdy fall delay 5.0 v 0 ns out 9 tdrdy0(dav) rdy fall to dav rise delay 5.0 v 115 ns out 10 twrdy rdy width 5.0 v 80 ns out 11 tdrdy0d(dav) rdy rise to dav fall delay 5.0 v 80 ns out notes: [1] 5.0 v 0.5 v
21 Z89165/166/167/168/169 dtad c ontrollers z ilog cp96tad0103 electrical characteristics Z89165/166 a/d converter a/d converter electrical characteristics v cc = 5.0v 10% parameter minimum typical maximum units resolution 8 bits integral non-linearity 0.5 1 lsb differential non-linearity 0.5 1 lsb zero error at 25 c 250 mv supply range 4.5 5.0 5.5 volts input voltage range va lo va hi volts conversion time 2 m sec input capacitance on ana 25 60 pf va hi range va lo +2.5 av cc volts va lo range an gnd av cc C2.5 volts va hi -Cva lo 2.5 av cc volts notes: voltage 4.5v C5.5v temp 0-70 c zilogs products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 telex 910-338-7621 fax 408 370-8056 internet: http://www.zilog.com ? 1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of mer- chantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document.
22 Z89165/166/167/168/169 dtad c ontrollers cp96tad0103 z ilog

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